#ifndef __UOTG_HOST_REGS_H_
#define __UOTG_HOST_REGS_H_

#ifdef __cplusplus
extern "C"{
#endif

#include "typedef.h"

////////////////////////////////////////////////////////////////////////////////////////////////////////////
typedef enum _ModeCfg
{
	  MOD_NORMAL
	, MOD_LOW_POWER
	, MOD_HIGH_SPEED
	, MOD_FORCED_FS
}ModeCfg;

//Host General Control Register
//Name: UOTGHS_HSTCTRL
//Address: 0x400AC400
//Access: Read-write
typedef union _HostCtrlReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 reserved0_7		: 8; 	// bit 0-7
		uint32 sofGenEnable		: 1; 	// bit 8, SOFE: Start of Frame Generation Enable
		uint32 sendReset		: 1; 	// bit 9, RESET: Send USB Reset
		uint32 sendResume		: 1; 	// bit 10, RESUME: Send USB Resume
		uint32 reserved11		: 1; 	// bit 11
		uint32 modeCfg			: 2; 	// bit 12-13, SPDCONF: Mode Configuration, Ref ModeCfg
		uint32 reserved14_31 	: 18; 	// bit 14-31 
	};
}HostCtrlReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Global Interrupt Status Register
//Name: UOTGHS_HSTISR
//Address: 0x400AC404
//Access: Read-only
typedef union _HostIntReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 wakeUpInt		: 1; 	// bit 0, HWUPI: Host Wake-Up Interrupt
		uint32 sofInt			: 1; 	// bit 1, HSOFI: Host Start of Frame Interrupt 
		uint32 upResumeInt		: 1; 	// bit 2, RXRSMI: Upstream Resume Received Interrupt 
		uint32 downResumeInt	: 1; 	// bit 3, RSMEDI: Downstream Resume Sent Interrupt
		uint32 resetSentInt		: 1; 	// bit 4, RSTI: USB Reset Sent Interrupt 
		uint32 devDisconnectInt	: 1; 	// bit 5, DDISCI: Device Disconnection Interrupt 
		uint32 devConnectInt	: 1; 	// bit 6, DCONNI: Device Connection Interrupt
		
		uint32 reserved7		: 1; 	// bit 7, RESET: Send USB Reset
		
		uint32 pep0				: 1; 	// bit 8, PEP_x: Pipe x Interrupt
		uint32 pep1				: 1; 	// bit 9, PEP_x: Pipe x Interrupt
		uint32 pep2				: 1; 	// bit 10, PEP_x: Pipe x Interrupt
		uint32 pep3				: 1; 	// bit 11, PEP_x: Pipe x Interrupt
		uint32 pep4				: 1; 	// bit 12, PEP_x: Pipe x Interrupt
		uint32 pep5				: 1; 	// bit 13, PEP_x: Pipe x Interrupt
		uint32 pep6				: 1; 	// bit 14, PEP_x: Pipe x Interrupt
		uint32 pep7				: 1; 	// bit 15, PEP_x: Pipe x Interrupt
		uint32 pep8				: 1; 	// bit 16, PEP_x: Pipe x Interrupt
		uint32 pep9				: 1; 	// bit 17, PEP_x: Pipe x Interrupt
		
		uint32 reserved18_24	: 7; 	// bit 18-24
		
		uint32 dma1 			: 1; 	// bit 25 
		uint32 dma2 			: 1; 	// bit 26 
		uint32 dma3 			: 1; 	// bit 27 
		uint32 dma4 			: 1; 	// bit 28 
		uint32 dma5 			: 1; 	// bit 29 
		uint32 dma6 			: 1; 	// bit 30 
		
		uint32 reserved31 		: 1; 	// bit 31 
	};
}HostIntReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Global Interrupt Clear Register
//Name: UOTGHS_HSTICR
//Address: 0x400AC408
//Access: Write-only
typedef union _HostIntClsReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 devConnectIntCls	: 1; 	// bit 0, DCONNIC: Device Connection Interrupt Clear
		uint32 devDisconnectIntCls: 1; 	// bit 1, DDISCIC: Device Disconnection Interrupt  Clear
		uint32 resetSentIntCls	: 1; 	// bit 2, RSTIC: USB Reset Sent Interrupt  Clear
		uint32 downResumeIntCls	: 1; 	// bit 3, RSMEDIC: Downstream Resume Sent Interrupt Clear
		uint32 upResumeIntCls	: 1; 	// bit 4, RXRSMIC: Upstream Resume Received Interrupt  Clear
		uint32 sofIntCls		: 1; 	// bit 5, HSOFIC: Host Start of Frame Interrupt  Clear
		uint32 wakeUpIntCls		: 1; 	// bit 6, HWUPIC: Host Wake-Up Interrupt Clear
		
		uint32 reserved7_31 	: 25; 	// bit 7-31 
	};
}HostIntClsReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Global Interrupt Set Register
//Name: UOTGHS_HSTIFR
//Address: 0x400AC40C
//Access: Write-only
typedef union _HostIntSetReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 devConnectIntSet	: 1; 	// bit 0, DCONNIC: Device Connection Interrupt Set
		uint32 devDisconnectIntSet: 1; 	// bit 1, DDISCIC: Device Disconnection Interrupt  Set
		uint32 resetSentIntSet	: 1; 	// bit 2, RSTIC: USB Reset Sent Interrupt  Set
		uint32 downResumeIntSet	: 1; 	// bit 3, RSMEDIC: Downstream Resume Sent Interrupt Set
		uint32 upResumeIntSet	: 1; 	// bit 4, RXRSMIC: Upstream Resume Received Interrupt  Set
		uint32 sofIntSet		: 1; 	// bit 5, HSOFIC: Host Start of Frame Interrupt  Set
		uint32 wakeUpIntSet		: 1; 	// bit 6, HWUPIC: Host Wake-Up Interrupt Set
		
		uint32 reserved7_31 	: 25; 	// bit 7-31 
	};
}HostIntSetReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Global Interrupt Mask Register
//Name: UOTGHS_HSTIMR
//Address: 0x400AC410
//Access: Read-only
typedef union _HostIntMskReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 devConnectIntEn	: 1; 	// bit 0, DDISCIE: Device Disconnection Interrupt Enable
		uint32 devDisconnectIntEn: 1; 	// bit 1, DCONNIE: Device Connection Interrupt Enable
		uint32 resetSentIntEn	: 1; 	// bit 2, RSTIE: USB Reset Sent Interrupt Enable
		uint32 downResumeIntEn	: 1; 	// bit 3, RSMEDIE: Downstream Resume Sent Interrupt Enable
		uint32 upResumeIntEn	: 1; 	// bit 4, RXRSMIE: Upstream Resume Received Interrupt Enable
		uint32 sofIntEn			: 1; 	// bit 5, HSOFIE: Host Start of Frame Interrupt Enable
		uint32 wakeUpIntEn		: 1; 	// bit 6, HWUPIE: Host Wake-Up Interrupt Enable
		
		uint32 reserved7		: 1; 	// bit 7, RESET: Send USB Reset
		
		uint32 pep0En			: 1; 	// bit 8, PEP_x: Pipe x Interrupt
		uint32 pep1En			: 1; 	// bit 9, PEP_x: Pipe x Interrupt
		uint32 pep2En			: 1; 	// bit 10, PEP_x: Pipe x Interrupt
		uint32 pep3En			: 1; 	// bit 11, PEP_x: Pipe x Interrupt
		uint32 pep4En			: 1; 	// bit 12, PEP_x: Pipe x Interrupt
		uint32 pep5En			: 1; 	// bit 13, PEP_x: Pipe x Interrupt
		uint32 pep6En			: 1; 	// bit 14, PEP_x: Pipe x Interrupt
		uint32 pep7En			: 1; 	// bit 15, PEP_x: Pipe x Interrupt
		uint32 pep8En			: 1; 	// bit 16, PEP_x: Pipe x Interrupt
		uint32 pep9En			: 1; 	// bit 17, PEP_x: Pipe x Interrupt
		
		uint32 reserved18_24	: 7; 	// bit 18-24
		
		uint32 dma1En 			: 1; 	// bit 25 
		uint32 dma2En 			: 1; 	// bit 26 
		uint32 dma3En 			: 1; 	// bit 27 
		uint32 dma4En 			: 1; 	// bit 28 
		uint32 dma5En 			: 1; 	// bit 29 
		uint32 dma6En 			: 1; 	// bit 30 
		
		uint32 reserved31 		: 1; 	// bit 31 
	};
}HostIntMskReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Global Interrupt Disable Register 
//Name: UOTGHS_HSTIDR
//Address: 0x400AC414
//Access: Write-only
typedef union _HostIntDisReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 devConnectInt	: 1; 	// bit 0, DDISCIE: Device Disconnection Interrupt Enable
		uint32 devDisconnectInt	: 1; 	// bit 1, DCONNIE: Device Connection Interrupt Enable
		uint32 resetSentInt		: 1; 	// bit 2, RSTIE: USB Reset Sent Interrupt Enable
		uint32 downResumeInt	: 1; 	// bit 3, RSMEDIE: Downstream Resume Sent Interrupt Enable
		uint32 upResumeInt		: 1; 	// bit 4, RXRSMIE: Upstream Resume Received Interrupt Enable
		uint32 sofInt			: 1; 	// bit 5, HWUPIEC: Host Wake-Up Interrupt Disable
		uint32 wakeUpInt		: 1; 	// bit 6, HWUPIEC: Host Wake-Up Interrupt Disable
		
		uint32 reserved7		: 1; 	// bit 7, RESET: Send USB Reset
		
		uint32 pep0			: 1; 	// bit 8, PEP_x: Pipe x Interrupt
		uint32 pep1			: 1; 	// bit 9, PEP_x: Pipe x Interrupt
		uint32 pep2			: 1; 	// bit 10, PEP_x: Pipe x Interrupt
		uint32 pep3			: 1; 	// bit 11, PEP_x: Pipe x Interrupt
		uint32 pep4			: 1; 	// bit 12, PEP_x: Pipe x Interrupt
		uint32 pep5			: 1; 	// bit 13, PEP_x: Pipe x Interrupt
		uint32 pep6			: 1; 	// bit 14, PEP_x: Pipe x Interrupt
		uint32 pep7			: 1; 	// bit 15, PEP_x: Pipe x Interrupt
		uint32 pep8			: 1; 	// bit 16, PEP_x: Pipe x Interrupt
		uint32 pep9			: 1; 	// bit 17, PEP_x: Pipe x Interrupt
		
		uint32 reserved18_24	: 7; 	// bit 18-24
		
		uint32 dma1 			: 1; 	// bit 25 
		uint32 dma2 			: 1; 	// bit 26 
		uint32 dma3 			: 1; 	// bit 27 
		uint32 dma4 			: 1; 	// bit 28 
		uint32 dma5 			: 1; 	// bit 29 
		uint32 dma6 			: 1; 	// bit 30 
		
		uint32 reserved31 		: 1; 	// bit 31 
	};
}HostIntDisReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Frame Number Register
//Name: Host Frame Number Register
//Address: 0x400AC420
//Access: Read-write
typedef union _HostFrameNumReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 dma4 			: 3; 	// bit 0-2, MFNUM: Micro Frame Number
		uint32 frameNum			: 11; 	// bit 3-13, FNUM: Frame Number
		uint32 reserved14_15	: 2; 	// bit 14-15
		uint32 frameLen			: 8; 	// bit 16-23, FLENHIGH: Frame Length
		uint32 reserved24_31 	: 8; 	// bit 31 
	};
}HostFrameNumReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
typedef struct _HostAddr
{
	uint8 address: 7; 		// bit 0-6, ? HSTADDRP3: USB Host 
	uint8 reserved	: 1; 	// bit 7, NXT_DSC_ADD: Next Descriptor Address
}HostAddr;
//Host Address 1 Register
//Name: UOTGHS_HSTADDR1
//Address: 0x400AC424
//Access: Read-write
typedef union _HostAddrReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 address0 	: 7; 	// bit 0-6, HSTADDRP0: USB Host Address
		uint32 reserved7	: 1; 	// bit 7
		uint32 address1		: 7; 	// bit 8-14, HSTADDRP1: USB Host Address
		uint32 reserved15	: 1; 	// bit 15
		uint32 address2		: 7; 	// bit 16-22, HSTADDRP2: USB Host Address
		uint32 reserved23	: 1; 	// bit 23
		uint32 address3 	: 7; 	// bit 24-30 , HSTADDRP3: USB Host Address
		uint32 reserved31	: 1; 	// bit 31
	};
}HostAddrReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Pipe Register
//Name: UOTGHS_HSTPIP
//Address: 0x400AC41C
//Access: Read-write
typedef union _HostPipeReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 pipe0En	: 1; 	// bit 0
		uint32 pipe1En	: 1; 	// bit 1
		uint32 pipe2En	: 1; 	// bit 2
		uint32 pipe3En	: 1; 	// bit 3
		uint32 pipe4En	: 1; 	// bit 4
		uint32 pipe5En	: 1; 	// bit 5
		uint32 pipe6En	: 1; 	// bit 6
		uint32 pipe7En	: 1; 	// bit 7
		uint32 pipe8En	: 1; 	// bit 8
		uint32 reserved9_15: 7; 	// bit 9-15
		
		uint32 pipe0Reset	: 1; 	// bit 16
		uint32 pipe1Reset	: 1; 	// bit 17
		uint32 pipe2Reset	: 1; 	// bit 18
		uint32 pipe3Reset	: 1; 	// bit 19
		uint32 pipe4Reset	: 1; 	// bit 20
		uint32 pipe5Reset	: 1; 	// bit 21
		uint32 pipe6Reset	: 1; 	// bit 22
		uint32 pipe7Reset	: 1; 	// bit 23
		uint32 pipe8Reset	: 1; 	// bit 24
		uint32 reserved25_31: 7; 	// bit 25-31
	};
}HostPipeReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//PipeType
typedef enum _PipeType
{
	PIPE_TYPE_CTRL = 0
	,PIPE_TYPE_ISO
	,PIPE_TYPE_BLK
	,PIPE_TYPE_INTRPT
}PipeType;

//PipeToken
typedef enum _PipeToken
{
	 PIPE_TOKEN_SETUP = 0
	,PIPE_TOKEN_IN
	,PIPE_TOKEN_OUT
}PipeToken;

//PipeSize
typedef enum _PipeSize
{
	 PIPE_SIZE_8 = 0
	,PIPE_SIZE_16
	,PIPE_SIZE_32
	,PIPE_SIZE_64
	,PIPE_SIZE_128
	,PIPE_SIZE_256
	,PIPE_SIZE_512
	,PIPE_SIZE_1024
	,PIPE_MAX
}PipeSize;

//PipeSize
typedef enum _PipeBank
{
	 PIPE_BANK_1 = 0
	,PIPE_BANK_2
	,PIPE_BANK_3
}PipeBank;

//Host Pipe x Configuration Register
//Name: UOTGHS_HSTPIPCFGx [x=0..9]
//Address: 0x400AC500
//Access: Read-write
typedef union _HostPipeCfgReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 reserved0		: 1; 	// bit 0
		uint32 isAllocMem		: 1; 	// bit 1, ALLOC: Pipe Memory Allocate
		uint32 pipeBank			: 2; 	// bit 2-3, PBK: Pipe Banks
		uint32 pipeSize			: 3; 	// bit 4-6, PSIZE: Pipe Size
		uint32 reserved7		: 1; 	// bit 7
		uint32 pipeToken		: 2; 	// bit 8-9, PTOKEN: Pipe Token
		uint32 autoSwitch		: 1; 	// bit 10, AUTOSW: Automatic Switch
		uint32 reserved11		: 1; 	// bit 11
		uint32 pipeType			: 2; 	// bit 12-13, PTYPE: Pipe Type
		uint32 reserved14_15	: 2; 	// bit 14-15
		uint32 pipeEpNum		: 4; 	// bit 16-19, PEPNUM: Pipe Endpoint Number
		uint32 pingEn			: 1; 	// bit 20, PINGEN: Ping Enable. This bit is relevant for High-speed Bulk-outtransaction only
		uint32 reserved21_23	: 3; 	// bit 21-23
		uint32 pipeIntReqFreq	: 8; 	// bit 24-31, INTFRQ: Pipe Interrupt Request Frequency, only for an Interrupt Pipe
	};
}HostPipeCfgReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Pipe x Status Register
//Name: UOTGHS_HSTPIPISRx [x=0..9]
//Address: 0x400AC530
//Access: Read-only
typedef union _HostPipeStatusReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 rxInDataInt		: 1; 	// bit 0, RXINI: Received IN Data Interrupt
		uint32 txOutDataInt		: 1; 	// bit 1, TXOUTI: Transmitted OUT Data Interrupt
		uint32 transSetupInt	: 1; 	// bit 2, TXSTPI: Transmitted SETUP Interrupt/UNDERFI: Underflow Interrupt
		uint32 pipeErrInt		: 1; 	// bit 3, PERRI: Pipe Error Interrupt
		uint32 nakInt			: 1; 	// bit 4, NAKEDI: NAKed Interrupt
		uint32 overflowInt		: 1; 	// bit 5, OVERFI: Overflow Interrupt
		uint32 rcvStalledOrCrcErrInt: 1; 	// bit 6, RXSTALLDI: Received STALLed Interrupt/RCERRI: CRC Error Interrupt
		uint32 shortPktInt		: 1; 	// bit 7, SHORTPACKETI: Short Packet Interrupt
		uint32 dataTogSeq		: 2; 	// bit 8-9, DTSEQ: Data Toggle Sequence, 0-DATA 0, 1-DATA 1
		uint32 reserved10_11	: 2; 	// bit 10-11
		uint32 busyBankNum		: 2; 	// bit 12-13, NBUSYBK: Number of Busy Banks
		uint32 curBank			: 2; 	// bit 14-15, CURRBK: Current Bank
		uint32 isAllowRW		: 1; 	// bit 16, RWALL: Read-write Allowed
		uint32 reserved17		: 1; 	// bit 17
		uint32 isCfgOk			: 1; 	// bit 18, CFGOK: Configuration OK Status
		uint32 reserved19		: 1; 	// bit 19
		uint32 pipeByteCount	: 11; 	// bit 20-30, PBYCT: Pipe Byte Count
		uint32 reserved31	: 1; 	// bit 31
	};
}HostPipeStatusReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Pipe x Clear Register
//Name: UOTGHS_HSTPIPICRx [x=0..9]
//Address: 0x400AC560
//Access: 0x400AC560
typedef union _HostPipeClsReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 rxInDataIntCls		: 1; 	// bit 0, RXINI: Received IN Data Interrupt
		uint32 txOutDataIntCls		: 1; 	// bit 1, TXOUTI: Transmitted OUT Data Interrupt
		uint32 transSetupIntCls		: 1; 	// bit 2, TXSTPI: Transmitted SETUP Interrupt/UNDERFI: Underflow Interrupt
		uint32 reserved3			: 1; 	// bit 3
		uint32 nakIntCls			: 1; 	// bit 4, NAKEDI: NAKed Interrupt
		uint32 overflowIntCls		: 1; 	// bit 5, OVERFI: Overflow Interrupt
		uint32 stalledOrCrcErrIntCls: 1; // bit 6, RXSTALLDI: Received STALLed Interrupt/RCERRI: CRC Error Interrupt
		uint32 shortPktIntCls		: 1; 	// bit 7, SHORTPACKETI: Short Packet Interrupt
		uint32 reserved8_31			: 24; 	// bit 8-31
	};
}HostPipeClsReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Pipe x Set Register
//Name: UOTGHS_HSTPIPICRx [x=0..9]
//Address: 0x400AC560
//Access: 0x400AC560
typedef union _HostPipeSetReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 rxInDataIntSet		: 1; 	// bit 0, RXINI: Received IN Data Interrupt
		uint32 txOutDataIntSet		: 1; 	// bit 1, TXOUTI: Transmitted OUT Data Interrupt
		uint32 transSetupIntSet		: 1; 	// bit 2, TXSTPI: Transmitted SETUP Interrupt/UNDERFI: Underflow Interrupt
		uint32 reserved3			: 1; 	// bit 3
		uint32 nakIntSet			: 1; 	// bit 4, NAKEDI: NAKed Interrupt
		uint32 overflowIntSet		: 1; 	// bit 5, OVERFI: Overflow Interrupt
		uint32 rcvStalledOrCrcErrIntSet: 1; // bit 6, RXSTALLDI: Received STALLed Interrupt/RCERRI: CRC Error Interrupt
		uint32 shortPktIntSet		: 1; 	// bit 7, SHORTPACKETI: Short Packet Interrupt
		uint32 reserved8_11			: 4; 	// bit 8-11
		uint32 busyBankNumSet		: 1; 	// bit 12, NBUSYBKS: Number of Busy Banks Set
		uint32 reserved13_31		: 19; 	// bit 13-31
	};
}HostPipeSetReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Pipe x Mask Register
//Name: UOTGHS_HSTPIPICRx [x=0..9]
//Address: 0x400AC560
//Access: 0x400AC560
typedef union _HostPipeMaskReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 rxInDataIntEn		: 1; 	// bit 0, RXINI: Received IN Data Interrupt
		uint32 txOutDataIntEn		: 1; 	// bit 1, TXOUTI: Transmitted OUT Data Interrupt
		uint32 transSetupIntEn		: 1; 	// bit 2, TXSTPI: Transmitted SETUP Interrupt/UNDERFI: Underflow Interrupt
		uint32 nakIntEn				: 1; 	// bit 4, NAKEDI: NAKed Interrupt
		uint32 overflowIntEn		: 1; 	// bit 5, OVERFI: Overflow Interrupt
		uint32 rcvStalledOrCrcErrIntEn: 1; 	// bit 6, RXSTALLDI: Received STALLed Interrupt/RCERRI: CRC Error Interrupt
		uint32 shortPktIntEn			: 1; 	// bit 7, SHORTPACKETI: Short Packet Interrupt
		uint32 reserved8_11			: 4; 	// bit 8-11
		
		uint32 busyBankIntEn		: 1; 	// bit 12, NBUSYBKE: Number of BusyBanks Interrupt Enable
		uint32 reserved13			: 1; 	// bit 13
		uint32 fifoCtrl				: 1; 	// bit 14, FIFOCON: FIFO Control
		uint32 reserved15			: 1; 	// bit 15
		uint32 pDishDmaEn			: 1; 	// bit 16, PDISHDMA: Pipe Interrupts Disable HDMA Request Enable
		uint32 pipeFreeze			: 1; 	// bit 17, PFREEZE: Pipe Freeze
		uint32 resetDataTog			: 1; 	// bit 18, RSTDT: Reset Data Toggle
		uint32 reserved19_31		: 13; 	// bit 19-31
	};
}HostPipeMaskReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Pipe x Disable Register
//Name: UOTGHS_HSTPIPIDRx [x=0..9]
//Address: 0x400AC620
//Access: Write-only
typedef union _HostPipeDisReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 rxInDataInt			: 1; 	// bit 0, RXINI: Received IN Data Interrupt
		uint32 txOutDataInt			: 1; 	// bit 1, TXOUTI: Transmitted OUT Data Interrupt
		uint32 transSetupInt		: 1; 	// bit 2, TXSTPI: Transmitted SETUP Interrupt/UNDERFI: Underflow Interrupt
		uint32 nakInt				: 1; 	// bit 4, NAKEDI: NAKed Interrupt
		uint32 overflowInt			: 1; 	// bit 5, OVERFI: Overflow Interrupt
		uint32 rcvStalledOrCrcErrInt: 1; 	// bit 6, RXSTALLDI: Received STALLed Interrupt/RCERRI: CRC Error Interrupt
		uint32 shortPktInt			: 1; 	// bit 7, SHORTPACKETI: Short Packet Interrupt
		uint32 reserved8_11			: 4; 	// bit 8-11
		
		uint32 busyBankInt			: 1; 	// bit 12, NBUSYBKE: Number of BusyBanks Interrupt Enable
		uint32 reserved13			: 1; 	// bit 13
		uint32 fifoCtrl				: 1; 	// bit 14, FIFOCON: FIFO Control
		uint32 reserved15			: 1; 	// bit 15
		uint32 pDishDma				: 1; 	// bit 16, PDISHDMA: Pipe Interrupts Disable HDMA Request Enable
		uint32 pipeFreeze			: 1; 	// bit 17, PFREEZE: Pipe Freeze		
		uint32 reserved18_31		: 14; 	// bit 18-31
	};
}HostPipeDisReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Pipe x Enable Register
//Name: UOTGHS_HSTPIPIERx [x=0..9]
//Address: 0x400AC5F0
//Access: Write-only
typedef union _HostPipeEnReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 rxInDataInt			: 1; 	// bit 0, RXINI: Received IN Data Interrupt
		uint32 txOutDataInt			: 1; 	// bit 1, TXOUTI: Transmitted OUT Data Interrupt
		uint32 txSetupOrUnderFlowInt: 1; 	// bit 2, TXSTPI: Transmitted SETUP Interrupt/UNDERFI: Underflow Interrupt
		uint32 pipeErrIntEn			: 1; 	// bit 3, PERRE: Pipe Error Interrupt Enable
		uint32 nakInt				: 1; 	// bit 4, NAKEDI: NAKed Interrupt
		uint32 overflowInt			: 1; 	// bit 5, OVERFI: Overflow Interrupt
		uint32 rxStalledOrCrcErrInt: 1; 	// bit 6, RXSTALLDI: Received STALLed Interrupt/RCERRI: CRC Error Interrupt
		uint32 shortPktInt			: 1; 	// bit 7, SHORTPACKETI: Short Packet Interrupt
		uint32 reserved8_11			: 4; 	// bit 8-11
		
		uint32 busyBankInt			: 1; 	// bit 12, NBUSYBKE: Number of BusyBanks Interrupt Enable
		uint32 reserved13			: 1; 	// bit 13
		uint32 fifoCtrl				: 1; 	// bit 14, FIFOCON: FIFO Control
		uint32 reserved15			: 1; 	// bit 15
		uint32 pDishDma				: 1; 	// bit 16, PDISHDMA: Pipe Interrupts Disable HDMA Request Enable
		uint32 pipeFreeze			: 1; 	// bit 17, PFREEZE: Pipe Freeze		
		uint32 reserved18_31		: 14; 	// bit 18-31
	};
}HostPipeEnReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Pipe x IN Request Register
//Name: UOTGHS_HSTPIPIERx [x=0..9]
//Address: 0x400AC650
//Access: Write-only
typedef union _HostPipeInReqReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 inReqNum			: 8; 	// bit 0-7, SINRQ: IN Request Number before Freeze
		uint32 inReqMode		: 4; 	// bit 8, NMODE: IN Request Mode
		
		uint32 reserved9_31		: 23; 	// bit 9-31
	};
}HostPipeInReqReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host Pipe x Error Register
//Name: UOTGHS_HSTPIPERRx [x=0..9]
//Address: 0x400AC680
//Access: Write-only
typedef union _HostPipeErrReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 dataTogErr		: 1; 	// bit 0, DATATGL: Data Toggle Error
		uint32 dataPidErr		: 1; 	// bit 1, DATAPID: Data PID Error
		uint32 pidErr			: 1; 	// bit 2, PID: PID Error
		uint32 timeOutErr		: 1; 	// bit 4, TIMEOUT: Time-Out Error
		uint32 crc16Err			: 1; 	// bit 5, CRC16: CRC16 Error
		uint32 errCounter		: 1; 	// bit 6, COUNTER: Error Counter
		
		uint32 reserved7_31		: 25; 	// bit 7-31
	};
}HostPipeErrReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host DMA Channel x Next Descriptor Address Register
//Name: UOTGHS_HSTDMANXTDSCx [x=1..7]
//Address: 0x400AC680
//Access: Read-write
typedef union _HostDmaAddrReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 nextDescAddr0		: 8; 	// bit 0-7, NXT_DSC_ADD: Next Descriptor Address
		uint32 nextDescAddr1		: 8; 	// bit 8-15, NXT_DSC_ADD: Next Descriptor Address
		uint32 nextDescAddr2		: 8; 	// bit 16-23, NXT_DSC_ADD: Next Descriptor Address
		uint32 nextDescAddr3	: 8; 	// bit 24-31, NXT_DSC_ADD: Next Descriptor Address
	};
}HostDmaAddrReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host DMA Channel x Address Register
//Name: UOTGHS_HSTDMANXTDSCx [x=1..7]
//Address: 0x400AC680
//Access: Read-write
typedef union _HostChnlAddrReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 buffAddr0	: 8; 	// bit 0-7, NXT_DSC_ADD: Next Descriptor Address
		uint32 buffAddr1	: 8; 	// bit 8-15, NXT_DSC_ADD: Next Descriptor Address
		uint32 buffAddr2	: 8; 	// bit 16-23, NXT_DSC_ADD: Next Descriptor Address
		uint32 buffAddr3	: 8; 	// bit 24-31, NXT_DSC_ADD: Next Descriptor Address
	};
}HostChnlAddrReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host DMA Channel x Control Register
//Name: UOTGHS_HSTDMANXTDSCx [x=1..7]
//Address: 0x400AC680
//Access: Read-write
typedef union _HostDmaCtrlReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 chnlEn			: 1; 	// bit 0, CHANN_ENB: Channel Enable Command
		uint32 loadNextChnlEn	: 1; 	// bit 1, LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command
		uint32 transEndEn		: 1; 	// bit 2, END_TR_EN: End of Transfer Enable (Control)
		uint32 buffEndEn		: 1; 	// bit 3, END_B_EN: End of Buffer Enable Control
		uint32 transEndIntEn	: 1; 	// bit 4, END_TR_IT: End of Transfer Interrupt Enable
		uint32 endOfBufIntEn	: 1; 	// bit 5, END_BUFFIT: End of Buffer Interrupt Enable
		uint32 descLoadIntEn	: 1; 	// bit 6, DESC_LD_IT: Descriptor Loaded Interrupt Enable
		uint32 burstLockEn		: 1; 	// bit 7, BURST_LCK: Burst Lock Enable
		uint32 reserved8_15		: 8; 	// bit 8-15
		uint32 buffLen			: 16; 	// bit 16-31, NXT_DSC_ADD: Next Descriptor Address
	};
}HostDmaCtrlReg;

////////////////////////////////////////////////////////////////////////////////////////////////////////////
//Host DMA Channel x Status Register
//Name: UOTGHS_HSTDMANXTDSCx [x=1..7]
//Address: 0x400AC680
//Access: Read-write
typedef union _HostChnlStatusReg
{
	 // raw register data 
	uint32 asUint32;
	 
	 // register bits 
	struct 
	{
		uint32 isChnlEn			: 1; 	// bit 0, CHANN_ENB: Channel Enable Status
		uint32 isChnlActive		: 1; 	// bit 1, CHANN_ACT: Channel Active Status
		
		uint32 reserved2_3		: 2; 	// bit 2-3, END_B_EN: End of Buffer Enable Control
		
		uint32 isTransEndEn		: 1; 	// bit 4, END_TR_IT: End of Transfer Interrupt Enable
		uint32 isEndOfBufEn		: 1; 	// bit 5, END_BUFFIT: End of Buffer Interrupt Enable
		uint32 descLoadIntEn	: 1; 	// bit 6, DESC_LD_IT: Descriptor Loaded Interrupt Enable
		
		uint32 reserved7_15		: 9; 	// bit 8-15
		uint32 buffCount		: 16; 	// bit 16-31, NXT_DSC_ADD: Next Descriptor Address
	};
}HostChnlStatusReg;

#ifdef __cplusplus
}
#endif

#endif


